Digital communications often require timing information to be extracted from a data stream. This data stream is subject to the degradation of the communication channel medium. Since the timing information is shared with the data, it is subject to inter-symbol interference (ISI). This ISI requires filtering to optimize the clock recovery performance, such as in U.S. Pat. No. 6,975,676. A general, known equalization circuit is shown in FIG. 1.
The adaptation of the timing recovery equalization towards an optimal configuration often requires extracting additional information and complex processing, such as using least-mean-square (LMS) algorithms. Similar requirements exist for the data recovery.
Many of these methods are based on optimization of the amplitude opening of the eye (that is, the eye diagram appearing on an oscilloscope display in which a digital data signal from a receiver is repetitively sampled and applied to the vertical input, while the data rate is used to trigger the horizontal sweep, and which is typically referred to as the vertical eye opening); however, often times it is desirable to obtain a maximum eye opening in the time dimension (typically referred to as the horizontal eye opening).
Different circuit topologies can be used to implement a timing recovery. For example, a known timing recovery circuit using delay control is shown in FIG. 2, and a known timing recovery circuit using a clock generation loop is shown in FIG. 3. Those skilled in the art will recognize that many other variations can be used.
Further circuits and methods are disclosed in U.S. Pat. Nos. 7,474,990 and 7,844,021, and United States Patent Application Publication No. 2008/0101515.
Known timing recovery and data recovery circuits for adapting the equalizer are complicated, however, resulting in significant power consumption and circuit area. Known methods focus on optimizing the vertical eye opening. Horizontal eye opening is, however, at least as important in many cases, especially for equalization of timing recovery circuits.
There is therefore a need for a method and apparatus to optimize equalization based on timing detection circuit outputs, and particularly one suitable for equalization not only of the timing recovery samples, but which can also be used for data equalization.